自己编写的一个小程序，功能是：时钟信号CLK1使数加1，CLK2使数减1，最后设置好的这个数要和一个给定的数进行大小比较。
可编译时报错，实在不知道怎么改：
Error: Can't resolve multiple constant drivers for net "D_OUT[7]" at zdz.vhd(15)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY zdz IS
  PORT(CLK1:IN STD_LOGIC;      --加1单脉冲
              CLK2:IN STD_LOGIC;      --减1单脉冲
                RST:IN STD_LOGIC;
                  DA :OUT STD_LOGIC;   --LED指示信号     
              DATA:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END zdz;
ARCHITECTURE behav OF zdz IS
  SIGNAL D_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL D_OUT: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
P1:PROCESS(CLK1,RST)                       
   BEGIN
        IF RST='1' THEN D_OUT<="10001000";
        ELSIF CLK1'EVENT AND CLK1='1' THEN
              D_OUT<=D_OUT+1;
        END IF;       
END PROCESS P1;
P2:PROCESS(CLK2,RST)                       
   BEGIN
        IF RST='1' THEN D_OUT<="10001000";
        ELSIF CLK2'EVENT AND CLK2='1' THEN
              D_OUT<=D_OUT-1;
        END IF;       
END PROCESS P2;
-----------------------------------------
   DATA<=D_OUT;
   D_IN<="10101010";
P3:PROCESS(D_OUT)                       
   BEGIN
        IF D_OUT > D_IN THEN DA<='1';
        ELSE DA<='0';
        END IF;        
END PROCESS P3; 
END behav;

上面的就是那个程序，还请帮忙给修改一下。谢谢了！

我改了一下，clk1和clk2为两个输入信号端，非时钟。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY zdz IS
  PORT(CLK1:IN std_logic;      --加1输入信号       
          CLK2:IN std_logic;      --减1输入信号
        RST:IN std_logic;
        DA :OUT std_logic;   --LED指示信号     
       DATA:OUT std_logic_vector(7 DOWNTO 0));
END zdz;
ARCHITECTURE behav OF zdz IS
  SIGNAL D_OUT: std_logic_vector(7 DOWNTO 0);
BEGIN
P1:PROCESS(CLK1,CLK2,RST)                       
   BEGIN
        IF RST='1' THEN D_OUT<="00001000";
        ELSIF clk1='1' THEN
              D_OUT<=D_OUT+1;
        ELSIF clk2='1' THEN
              D_OUT<=D_OUT-1;
        END IF;       
END PROCESS P1;
-----------------------------------------
P3:PROCESS(D_OUT)
VARIABLE D_IN : STD_LOGIC_VECTOR(7 DOWNTO 0):="00001000";                      
   BEGIN
        IF D_OUT > D_IN THEN DA<='1';
        ELSE DA<='0';
        END IF;        
END PROCESS P3;
 DATA<=D_OUT;
END behav;